In the LSI manufacturing process, it is important to equalize the metal density (i.e. a ratio of metal for the chip area) as one requirement to suppress the manufacturing dispersion. For example, when the metal density is not equalized, the heights of the wirings vary after the Chemical Mechanical Planarization (CMP) process, as depicted in FIG. 33. In the example of FIG. 33, several wirings 3001 are formed in an insulator 3003. However, compared with a dotted line 3005 as a reference, it is understood that the wirings on the left side are rarely cut, but the wirings on the right side are deeply cut. Thus, it is not preferable that the heights of the wirings vary.
In order to equalize the metal density, the insertion of the dummy metal has conventionally been carried out. The insertion of the dummy metal is to enable the metal density to be within a certain range by, when there is an area in which the density of the wirings 3001 is low, as depicted in FIG. 34A, inserting dummy metal pieces 3007 into such an area, as depicted in FIG. 34B.
There is a first conventional method of inserting the dummy metal, which includes (a) determining the layout of the wirings, (b) inserting the dummy metal, (c) verifying the timing, (d) correcting the layout and (e) manufacturing (i.e. process) in this order. In addition, there is also a second conventional method, which includes (a) determining the layout of the wirings, (b) verifying the timing, (c) correcting the layout, (d) inserting the dummy and (e) manufacturing (i.e. process) in this order.
In the first conventional method, because the dummy metal is inserted during the design and the timing in the circuit into which the dummy metal was inserted is verified, the size of data used for the timing verification becomes large. However, because the timing verification is carried out for the circuit into which the dummy metal was inserted, it is possible to accurately carry out the timing verification. In addition, it becomes possible to optimize the timing and the dispersion of the wiring heights after taking into account the layout.
On the other hand, in the second method, because the dummy metal is inserted after the timing verification according to the design rule, the size of data used for the timing verification can be small. However, because the timing verification in which any margin is taken into account is carried out for the circuit without the dummy metal, the accuracy of the second method is lower than that of the first method. In addition, because the layout is not taken into account, the optimization cannot be carried out.
In the aforementioned techniques, when a method in which the dummy metal is inserted after the layout of the circuit is fixed is adopted, it is impossible to raise the accuracy of the timing verification. On the other hand, because the data size of the circuit layout data is already large before inserting the dummy metal due to development of the microfabrication and enlargement of the circuit, it is preferable to avoid that the data size is made larger due to the insertion of the dummy metal during the design.